///////////////////////////////////////////////////////////////////////////////
// Company: Altera
// Author: Altera
//
// Created Date: Unknown
// Design Name:
// Module Name: regn
// Project Name: Proc
// Target Devices: Cyclone II EP2C20F484C7
// Tool Versions: Quartus 13.0
// Description: A clocked register module that will load in a new input if the
//    input signal is high. Otherwise it will retain its current value across 
//    each clock cycle.
// 
// Dependencies: None
// 
// Revision:
// 0.01 - File Ported from Altera code
//
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////
module regn(R, Rin, Clock, Q, Resetn);

	/* Parameters */
	parameter n = 9;       // 9-bit reg/bus size
	
   /* Inputs */
   input [n-1:0] R;       // Input signal
	input Rin, Clock, Resetn;      // Control signal & Processor Clock
	
	/* Outputs */
   output reg [n-1:0] Q;  // Register out
	
	initial begin
		Q = 0;//9'b111111111;
	end
	
	/* Load new value if signal is high */
	always @(posedge Clock) begin		
		if (Rin == 1)
			Q = R;
	end
			
endmodule
